High data reliability, high speed of memory access, reduced chip size and reduced power consumption are features that are demanded from semiconductor memory. To achieve reduced power consumption and higher memory access speed, a redistribution layer (RDL), a metal layer that provides low impedance and high conductivity has been increasingly used in semiconductor memory devices, to couple, for example, pads and data queue circuits (or data input/output circuits) across layers. Thin package products including multiple chips stacked thereon have been increasingly used. In a thin package product, the RDL increases the thickness of a laminated material on a board.
To construct a package or chip stack with a reduced height, the thickness of each chip must be reduced. To reduce the thickness of each chip to achieve a desired chip thickness, a back surface of a wafer that provide chips may be processed by a back grinding process. Because the thickness of the RDL accounts for approximately 10% of the entire chip thickness, distortion of the RDL that affects the warpage of the chip becomes non-negligible as the wafer is thinned by back grinding. Thus, the thickness of a wafer providing chips has been reduced as desired, the warpage of the chip in the product due to the distortion of the RDL has become a major problem.
For example, forming a thin film on a flat wafer creates a mechanical stress applied to the wafer, and to reduce this stress, the wafer warps. FIG. 1 is a schematic diagram of warpage of a wafer and a thin film in a conventional semiconductor device while forming the thin film on the wafer. First, the thin film is formed in a high-temperature as shown in the top. After the thin film is formed, an ambient temperature of the wafer with the film is lowered to a room temperature, as shown in the middle. Because there is a difference in coefficient of thermal expansion (CTE) between the wafer and the thin film, the difference in CTE causes the wafer to be distorted in a manner to bend towards the thin film, which causes the stress on the thin film and the thin film also becomes distorted as shown in the bottom.
FIG. 2 is a layout diagram of wiring layers of RDLs 6 in a conventional semiconductor device 5. The conventional semiconductor device 5 is a chip. The wiring layers of RDLs 6 are connected to major power supply lines, such as a power supply voltage line and a ground voltage line. Some other power supply lines (e.g., a partial power supply voltage VDD2, etc.) are also be connected to the wiring layers of RDLs 6, but they are thinner than the major power supply lines. When pads 24a are arranged along an upper side 2a and pads 24b are arranged on a lower side 2c of the chip 5, the wiring layers of RDLs 6 coupled to the pads 24a and 24b inevitably have an elongated shape extending in a first direction of 7a along sides 2b and 2d, perpendicular to and longer than the sides 2a and 2c extending in a second direction 7b. Thus, the wiring layers of RDLs 6 supply the power supply voltages from the pads 24a and 24b to an array of internal elements. Being thick RDLs in an uppermost layer close to the surface of the chip 5, the wiring layers of RDLs have stress greater than stresses of internal metal layers (i.e. lower layers made of aluminum or copper etc.) of the chip 5. When the wiring layers of RDLs 6 are elongated in the first direction 7a, therefore, the large stress of the wiring layers of RDLs 6 pull the upper and lower pads 24a and 24b toward each other. The wafer warps along the first direction 7a of the chip 5. Even if the chip 5 is in a square shaper, stress arises in the direction of the uppermost wiring layers of the RDLs, causing the wafer to warp towards the surface of the chip 5.
FIG. 3A is a layout diagram of wiring layers of RDLs with a dicing diagonally rotated in a wafer plane with respect the wiring layer of RDLs in a conventional semiconductor device. FIG. 3B is a schematic diagram of warpage in the conventional semiconductor device. Dicing the wafer along 45-degree dicing lines as shown in FIG. 3A results in the diagonal warpage of the chip as shown in FIG. 3B. Diagonal corners close to longer wiring layers of the RDLs tend to have greater warpages whereas the other two diagonal corners closet to shorter wiring layers of the RDLs tend to have less warpages. The greater diagonal warpage close to the longer wiring layers of the RDLs is caused by stress along the direction of a pattern of RDLs wiring layers and other patterns in the chip not by the chip shape.
FIG. 4A is a layout diagram of an uppermost wiring layer in a conventional semiconductor device 45. FIG. 4A is a plan view of the uppermost wiring layer of the conventional semiconductor device 45. The semiconductor device 45 may have sides 40a to 40d. The sides 40b and 40d opposite to each other with respect to the conventional semiconductor device 45, extending in a first direction 47a. The sides 40a and 40c opposite to each other with respect to the semiconductor device 45, extending in a second direction 47b, which is perpendicular to the first direction 47a. The semiconductor device 45 including the uppermost wiring layer is a one-channel mobile dynamic random access memory (DRAM). The uppermost wiring layer of the semiconductor device 45 includes a plurality of pads 44, such as power terminals or data terminals, which are arranged in the second direction 87b along the side 40a extending in the first direction. The uppermost wiring layer of the semiconductor device includes wiring layers 461 and 462 made of redistribution layers (e.g., internal redistribution layers (iRDL)) extending along the first direction 47a in parallel to the sides 40b and 40d. The wiring layers 461 is coupled to a power supply wire for providing a power supply voltage VDD from a power pad that receives the power supply voltage VDD. The wiring layers 462 is coupled to another power supply wire for providing a power supply voltage VSS (e.g., a ground voltage) that is lower than the power supply voltage VDD from another power pad that receives the power supply voltage VSS. The power supply wiring layers 461 and 462 for providing the power supply voltage VDD and VSS may have greater thicknesses than other power supply wires (e.g., power supply wire that provides a partial power supply voltage VDD2) that are coupled to another wiring layers of RDLs. The warpage due to the stress along the wiring layers of RDLs 461 and 462 extending from the side 40a to the side 40c along the sides 40b and 40c in the first direction 47a are great and non-negligible as explained earlier. FIG. 4B is a schematic diagram of the uppermost wiring layer in the conventional semiconductor device 45.
As described above, the warpage is affected by physical property of the wafer, the aspect ratio of the chip, and the direction of layout patterns. Because the RDLs and a passivation layer made of polyimid (PI) and covering the RDL, both having greater thicknesses extend in the uppermost layer closer to the surface, stress and distortions of the PI layer and the RDL affect greatly to the warpage of a semiconductor device. Thus, a greater thickness of the RDL distorts the chip that is undesirable to reduce the chip size in thickness.